Jay Sonawane

Hello! and welcome to my corner of the internet:D

I am a Ph.D. student in Electrical and Computer Engineering at Georgia Institute of Technology. My research focuses on BEOL oxide-channel and ferroelectric devices for monolithic /heterogenous 3D integration, advised by Prof. Shimeng Yu at the Laboratory for Emerging Circuits and Devices.

During my undergraduate program, I specialized in Nanoelectronics and Integrated Ciruits, at Indian Institute of Technology Bombay pursuing a Dual Degree (B.Tech+M.Tech) in Electrical Engineering.

I was involved in research with the MeLoDe (Memory Logic Device and Design) group, with Prof. Udayan Ganguly and Prof. Veeresh Deshpande. My Dual Degree thesis was based on BEOL compatible ITO transistor fabrication and modeling for monolithic 3D integration, where I fabricated some cool ITO transistors. Earlier I worked on TCAD modeling of GF32nm SOI MOSFET for application in band-to-band tunneling neuron. Besides, I worked on the integration of variability-aware process and aging degradation device-to-circuit degradation in CARAT, under the guidance of Prof. Souvik Mahapatra.

Amidst the boundless expanses of academic research, I have developed a fervent fascination for Logotherapy. In the quest for comprehending the intricacies of human belief systems and behavioral science, I find myself drawn to delve into the schools of philosophy.

Research Interests

An enduring fascination with nanoscale devices fuels my profound academic passion for nanoelectronics, device physics, and modeling. I am interested in designing and fabrication of novel devices with accurate modeling, for efficient device-to-circuit system level translation.

• Heterogenous/Monolithic 3D Integration
• Compute-in-Memory, Emerging Non-Volatile Memories (eNVMs), AI Hardware
• Device-to-circuit translation, Design Technology Co-Optimization
• Device, Circuit Reliability and Variability

Experience and Teaching Responsibilities

Here’s an essence of my research and other key projects, and professional work experience.

Coordinator, SEMIX IIT Bombay, 2023-24

Teaching Assistant | Department of Electrical Engineering, IIT Bombay
» EE 724 - Nanoelectronics, Fall 2024, Prof. Udayan Ganguly (Mentored 2 out of the best 4 project teams, course and projects in collaboration with Synopsis)
» EE 746 - Neuromorphic Engineering, Fall 2023, Prof. Udayan Ganguly (Co-mentored 2 team projects on CMOS-based neuron operation simulation)

Department Academic Mentor, Electrical Engineering, 2022-23

Convener, Electronics and Robotics Club, IIT Bombay, 2020-21

Updates

Date	News
June 2024	Presented my Master's project on BEOL-compatible ITO transistor fabrication and modeling for heterogeneous 3D integration.
February 2024	Received GRA offer from Prof. Shimeng Yu. Will be an incoming Ph.D. student at Georgia Institute of Technology.
February 2024	Fabricated back-gated transistor: ITO BG-FET using ALD, RF sputtering and 2 optical lithography levels. The transistor leakage is very low (1e-12 A/um)
December 2023	Fabricated my first transistor: ITO Ring-FET using ALD, RF sputtering and 1st level optical lithography. The transistor has an incredible S/D Ioff of 5e-17 A/um and SS of 69.9 mV/dec
November 2023	Submitted my first journal paper titled "Design Space and Variability Analysis of SOI MOSFET for Ultra-Low Power Band-to-Band Tunneling Neurons" to the IEEE Transactions on Electronic Devices.
August 2023	Started my Master's project on BEOL-compatible ITO transistor fabrication and modeling for heterogeneous 3D integration with Prof. Veeresh Deshpande.
May 2023	Started a research project on process and aging variability-aware degradation in CARAT with Prof. Souvik Mahapatra on the topic: Reliability of Cryo CMOS.
June 2023	Received my first conference rejection (SISPAD 2023) ;p
May 2023	Received the Undergraduate Research Award 01 (URA 01) for "excellent contribution to research in preliminary research/developmental exposure" for my project: "TCAD calibration of SOI MOSFET followed by design space exploration for energy-efficient neurons."
April 2023	Submitted my first conference paper titled "7.5× Energy Reduction by Engineering SOI MOSFET Design for Ultra-Low Power Neurons Using Experimentally Calibrated TCAD" to SISPAD 2023.
May 2022	Joined Atomberg Technologies as a Research and Development Engineer intern.
May 2022	Started research with Prof. Udayan Ganguly in the SOXI, Variability, FeRAM subgroup of the MeLoDe lab.
December 2021	Returned to campus after a 2-year COVID break.
June 2021	Started the Summer Undergraduate Research Program (SURP) with Prof. Souvik Mahapatra on the topic: Reliability of Cryo CMOS.
May 2021	Interned as a Data Scientist at Carnot Technologies.
June 2020	Selected as the convener of the Electronics and Robotics Club, IIT Bombay.
July 2019	Started my undergraduate studies in Electrical Engineering at IIT Bombay.