A six-transistor cell you can read, write and resize. Every panel on the bench runs from the same transistor model, so a change in one place shows up in the waveforms, the margins and the butterfly curve together.
Two inverters hold each other in place: that is the stored bit. Two access transistors (PG) connect the pair to the bitlines when the wordline goes high. Wire colour follows voltage, warm for high and cool for low. A transistor that is conducting turns green, shows its current, and dots run along the path the current takes.
Model: long-channel EKV transistors, PMOS at 0.6 times NMOS drive per unit strength, 0.2 fF per storage node, 0.1 fF of bitline per cell plus 3 fF. Random variation follows Pelgrom scaling: a transistor k times stronger varies 1/√k as much. The numbers build intuition. They are not any foundry's device data.
A read disturbs the node holding 0. With the wordline high, the bitline pushes current into it. PG and PD form a divider, so that node rises by a bump. If the bump reaches the other inverter's trip point, the cell flips while being read. The cell ratio β = PD ÷ PG sets the bump. Bigger is safer.
A write starts from the other node, the one holding 1. A bitline is pulled low and PG has to drag that node below the trip point while PU keeps feeding it. The pull-up ratio γ = PU ÷ PG sets who wins. Smaller is easier to write.
A stronger access transistor speeds reads and helps writes, and it makes the read bump worse. FinFETs made this harder because strength comes in whole fins: the dense cell is 1:1:1. Assist circuits and, since nanosheets, adjustable sheet width are how designers get the margin back.
Try it on the bench: load Read fails, press Read and use Play one phase to watch the bump cross the trip point and the stored bit flip. Then add wordline underdrive until it survives. Load Write fails and rescue it with negative bitline.
The second plot on the bench follows Section 3 of Shimeng Yu's ECE 6465 at Georgia Tech: static noise margin from the butterfly curve, the N-curve, dynamic stability, leakage, then variability. His slides call the storage nodes N1 and N2 and number the transistors 1 and 2; here they are Q and QB, left and right.
Lower the NMOS and PMOS thresholds together and the read current rises, the write gets easier, and the standby leakage climbs about ten times for every 70 mV. Higher thresholds do the reverse. Open Transistor Id–Vg and move the Vt sliders, or load the low-Vt and high-Vt presets.
Shift a single threshold and the two lobes stop matching, so SNM = min[SNM left, SNM right]. The butterfly shows noise between the two nodes, which is what mismatch is. Which Vt matters ranks the six transistors. The N-curve shows the same shift as a change in SVNM and in SINM, the current needed to tip the cell.
Static margins assume the noise lasts for ever. That is pessimistic for a read and optimistic for a write. On the butterfly views the black line is the path the two nodes actually took; a write succeeds only if it crosses the diagonal before the wordline closes. The crossing time grows with γ, so load Write too short to see a write that passes the static test and still fails.
Random dopant fluctuation, line-edge roughness and metal work-function variation make transistors that are identical on paper differ in silicon. Random telegraph noise moves Vt from moment to moment, and negative-bias temperature instability raises the PMOS threshold over years: the aged pull-up preset mimics it. SRAM suffers most because it uses the smallest transistors and its read never reaches full logic levels.
On a Pelgrom plot, the spread of Vt grows as 1 ÷ √(W·L). The bench applies the same rule: a transistor twice as strong gets 1 ÷ √2 of the spread. Monte Carlo draws 240 cells and counts how many sigma separate the mean margin from failure. Margins vs VDD shows the 3σ cell running out long before the nominal one, which sets the array's minimum voltage.
A steeper sub-threshold slope allows a lower Vt at the same leakage, and variation from dopants shrinks: in 14 nm FinFETs line-edge roughness and work-function variation dominate. The price is width in whole fins and harder threshold tuning, which is why the dense cells in those nodes are fixed at 1:1:1 or 1:2:2.
Try it: press Random cell a few times and watch the butterfly, then Read 3σ and lower VDD until the read upsets. The transient on the bench uses the same shifted thresholds, so a cell that fails on the plot also fails in the animation, unless the operation is short enough to escape.
This is a 64-bit memory: 8 wordlines by 8 bitline pairs, holding 16 words of 4 bits. A 2:1 column mux lets two words share each row, which keeps the array closer to square and gives each sense amplifier twice the cell pitch to fit in. Contents are example data.
Every cell on the active row connects to its bitlines, including the cells of the other word. Those half-selected cells go through a read they did not ask for, on every access. Read stability has to hold for them too.
One small cell has to discharge a wire shared by hundreds of others, so nobody waits for a full swing. A sense amplifier fires at roughly 100 mV of difference. On the bench, change the cells on the bitline and watch the read time move.
With a column mux, neighbouring cells belong to different words. A particle strike that upsets two adjacent cells then causes one bit error in each of two words, which single-bit correction can repair.
The published bitcell area is only the cell. A usable memory also needs wordline decoders and drivers, precharge, column muxes, sense amplifiers, write drivers, assist circuits and timing. Array efficiency is the share of the macro that is actually bitcells, and macro density in Mb/mm² is what a chip designer really gets.
Each bitline segment needs its own column circuits. At N2, TSMC doubled the cells per bitline from 256 to 512 and reported close to 10% more density. Set the slider from 256 to 512 and the model lands on about the same gain.
From 7 nm to 5 nm, TSMC quoted 1.84× logic density and 1.35× SRAM density. In 2025 Synopsys matched the 38.1 Mb/mm² of the new 2 nm class macros on 3 nm FinFETs by reworking level shifters in the periphery, at less than half the speed.
On TSMC's 20 nm macro the read-assist circuit cost 1.2% of area and write assist 3.7%. Intel keeps backside power out of the 18A bitcell because it would enlarge the cell by 10%, and uses it under the periphery instead.
The 6T cell shrank about 10,000 times between 1987 and 2025 and then nearly stopped. On Intel products SRAM takes roughly 10% to 50% of the die depending on the market.
| NODE | TRANSISTOR AND SUPPLY | 6T BITCELL, µm² | ARRAY, PERIPHERY AND ASSIST | ON-CHIP MEMORY AT THIS NODE |
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Node names stopped describing a physical dimension around 22 nm, so compare cells by area, not by name. Product cache sizes are the manufacturers' published specifications. The TSMC 65, 45, 20 and 16 nm cell areas and the Hitachi HM6147 entry are the figures from the original conference papers and data sheets and were not re-checked against a linked source for this page. TSMC's N2 cell is listed at 0.021 µm² as reported from ISSCC 2025; earlier press estimates near 0.0175 µm² were worked backwards from the density figure.