Why does CMOS use an n⁺⁺ polysilicon gate on the NMOS and a p⁺⁺ polysilicon gate on the PMOS, and what replaced them after 45 nm? Move each gate's workfunction or add an interface dipole, and watch the energy band diagram and the threshold voltage respond. Pick a technology node to load a typical gate stack from 180 nm to 2 nm.
Model: ideal MOS capacitor with Qox = 0, ni = 10¹⁰ cm⁻³, kT/q = 25.85 mV, χSi = 4.05 eV, Eg = 1.12 eV (Ei at mid-gap), χSiO₂ = 0.95 eV, χHfO₂ ≈ 2.0 eV, εSi = 11.7ε₀, εox = 3.9ε₀ (high-k entered as EOT). Degenerate poly has EF at the band edge: n⁺⁺ Φm = 4.05 eV, p⁺⁺ Φm = 5.17 eV. VFB = Φm − Φs + ΔVdip. The band diagram solves the 1-D Poisson charge relation for ψs; the VT formula uses the depletion approximation (ψs = 2φF). In thin-body mode the depletion charge is capped at qN·Tsi and the gate is treated as single-sided; real FinFET/GAA devices are multi-gate and define VT by a current criterion, so treat those numbers as trends. Node presets are textbook-typical stacks, not any foundry's actual process; poly depletion, quantum confinement and short-channel VT roll-off are ignored. The oxide is drawn wider than scale.