MOS capacitor · 300 K · Si / SiO₂ · C–V characterisation

MOS C–V Lab

Build a MOS capacitor on p- or n-type silicon, then add the defects you find in real devices: fixed oxide charge (and where it sits), an interface dipole, interface traps (D_it), deep traps in the silicon, slow border traps and mobile ions. Change the measurement frequency, sweep rate and sweep direction, and read the C–V curve the way you would in the lab. The quick setups at the bottom load common cases and explain what to look for.

C–V curve

forward sweep (V_min → V_max) reverse sweep (V_max → V_min) ideal, high frequency ideal, quasi-static probe bias (band diagram)

Band diagram at probe

Conductance G_p/ω at probe

V_FB vs EOT

A thickness series separates the two kinds of shift. Charge in the oxide changes the slope (−Q/ε_ox). Workfunction and dipole set the intercept at EOT = 0.

What you would extract from this curve

from the forward sweep, compared with the ideal device

Quick setups

Each button loads a full set of parameters. Change anything afterwards.

Reading hysteresis in a dual sweep

Both sweeps start at V_min, go to V_max and come back. What matters physically is which way the reverse curve moved. Clockwise or counterclockwise then depends on the substrate, because a p-type C–V falls from left to right and an n-type C–V rises.

Physical cause	Charge left behind after the +V end	Reverse curve moves	p-type loop	n-type loop
Charge trapping from the silicon: border traps or oxide traps near the interface capture electrons at +V (or holes at −V)	negative	to the right (+V)	counterclockwise	clockwise
Mobile ions (Na⁺, K⁺) drifting to the Si interface at +V, ferroelectric polarisation, or charge injected from the gate	positive (or ions moved closer to Si)	to the left (−V)	clockwise	counterclockwise

Change the sweep rate. Trapping hysteresis shrinks at fast sweeps (the traps cannot keep up) and also at very slow ones only if the traps reach equilibrium both ways. Ion drift is strongly temperature-activated, so a bias-temperature stress at 150–250 °C that shifts V_FB by −qN_m/C_ox is the classic test for mobile ions.
Change the sweep range. Trapping hysteresis grows as V_max pushes the surface Fermi level through more traps. With border traps, the width tracks how far E_F moves at the interface.
Direction check for ferroelectrics. A ferroelectric gate gives the same direction as mobile ions (clockwise on p-type), and a memory window that scales with the coercive voltage, not with temperature.
Interface traps alone give no hysteresis. Fast D_it follows the sweep, so it stretches the curve along V and adds frequency dispersion, but forward and reverse coincide.

Model: 1-D MOS capacitor at 300 K, exact Poisson charge for Si (n_i = 10¹⁰ cm⁻³, E_g = 1.12 eV, χ = 4.05 eV, ε_Si = 11.7ε₀, ε_ox = 3.9ε₀). Minority carriers answer the ac signal with a response time τ_R: factor 1/(1+ω²τ_R²). Interface traps use a continuum response arctan(ωτ)/ωτ with τ = 1/(σv_th(n_s+p_s)), σ = 10⁻¹⁶ cm², v_th = 10⁷ cm/s. Bulk deep traps follow the dc bias and answer the ac signal with 1/(1+ω²τ_e²). Border traps and mobile ions are slow state variables integrated along the sweep. The oxide potential is drawn linear, ignoring kinks at charge sheets. Series resistance, leakage and quantum effects are not modelled.